1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method.
2. Description of the Related Art
A semiconductor device manufacturing process includes a process for forming semiconductor elements such as transistors on/in a semiconductor substrate, and a wiring process for forming a wiring pattern via an interlayer insulation film above semiconductor elements such as transistors. Wirings are often formed in multi-layers. The process for forming a wiring pattern of each layer includes a film formation process, a photolithography process, an etching process, and other processes. In some cases, an unintentional short defect portion may be formed on a wiring pattern due to dust or the like generated from the semiconductor manufacturing devices used in those steps.
In a semiconductor device manufacturing process, defect inspection for detecting an unintentional short defect portion is conducted after wiring pattern formation. Such defect inspection is conducted in order to check whether or not the density of short defect portions is within a permissible level. This defect inspection is employed for the purpose of controlling the quality of semiconductor devices or monitoring the condition of dust in each device. Defect inspection is used not only just for production control but also to repair, using inspection results, an unintentionally formed short defect portion.
Japanese Patent Laid-Open No. 11-25853 has disclosed that a short defect portion 2 of a silver electrode 1 formed on a glass substrate 9 of a plasma display is removed by processing with laser beams, as illustrated in FIG. 2A of Japanese Patent Laid-Open No. 11-25853.
Japanese Patent Laid-Open No. 9-082806 has disclosed that the short-circuited part between power source wirings 8b1 and 8b2 is separated from a power source wiring system in a power source wiring block 7 by a focused ion beam (FIB) cutting at cut points C1 to C4 as illustrated in FIG. 13 of Japanese Patent Laid-Open No. 9-082806.
In the case of using laser beams, it is considered difficult to remove a short defect portion of a wiring pattern in a semiconductor device at the submicron level. The use of a focused ion beam, on the other hand, enables a short defect portion of a wiring pattern in a semiconductor device to be removed at the submicron level.
With the technique disclosed in Japanese Patent Laid-Open No. 9-082806, however, wiring patterns or insulation films around or below the cut points C1 to C4 may be damaged by ion irradiation.